-- $Id: $
-- File name:   SHIFTBACK.vhd
-- Created:     11/28/2010
-- Author:      Alyssa Welles
-- Lab Section: 4
-- Version:     1.0  Initial Design Entry
-- Description: SHIFT REGISTER for the Transmitter


LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_unsigned.ALL;

entity SHIFTBACK is
  port(
          CLK : in std_logic;
        RST_N : in std_logic;
 SHIFT_ENABLE : in std_logic;
     RCV_DATA : in std_logic_vector (7 downto 0);
   SHIFT_UPDT : in std_logic;
    NEWPACKET : in std_logic;
       D_ORIG : out std_logic
       );
end SHIFTBACK;



ARCHITECTURE dataflow OF SHIFTBACK IS
 signal val, nextval : std_logic_vector(7 downto 0);


BEGIN
   REG_SHFT: process (CLK, RST_N)
   begin
    if (RST_N = '0') then
      val <= (others => '0');
    elsif (CLK'event and CLK = '1') then      
      val <= nextval;
    end if; 
   end process;
   
   
   nxstlog: process(SHIFT_ENABLE, SHIFT_UPDT, val, NEWPACKET, RCV_DATA(7 downto 0))
   begin
    if NEWPACKET = '1' then
      nextval <= RCV_DATA(7 downto 0); 
    elsif (SHIFT_ENABLE = '1' AND SHIFT_UPDT = '1') then
      nextval <= val(6 downto 0) & '0';
    else
      nextval <= val;
    end if;
   end process nxstlog; 
   
   D_ORIG <= val(7);

end dataflow;



